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Verilog/VHDL by eejlny on Aug 26, 2009			eejlny Posts: 3 Joined: Mar 2, 2006 Last seen: Aug 20, 2017
Hello, I am interested in joining the development and I have developed a high-performance programmable and configurable motion estimation engine mapped to an FPGA which runs under x.264. Now my work is in VHDL but I see that you have selected Verilog. Why do you want to restrict yourself to a single language?. Successful open-source projects such as the Leon3 SPARC processor include components in Verilog/VHDL and FPGA synthesis and P&R tools will compile both of them with no problems. I think to open the language to both VHDL/Verilog will be a good idea for a complex project such as this one. Regards Jose Hello, I am interested in joining the development and I have developed a high-performance programmable and configurable motion estimation engine mapped to an FPGA which runs under x.264. Now my work is in VHDL but I see that you have selected Verilog. Why do you want to restrict yourself to a single language?. Successful open-source projects such as the Leon3 SPARC processor include components in Verilog/VHDL and FPGA synthesis and P&R tools will compile both of them with no problems. I think to open the language to both VHDL/Verilog will be a good idea for a complex project such as this one. Regards Jose

RE: Verilog/VHDL by gil_savir on Aug 26, 2009			gil_savir Posts: 59 Joined: Dec 7, 2008 Last seen: May 10, 2021
I think that we are also limited by the open-source eda tools that exist. I know there is open Verilog simulator (Icarus). I don't know which open tools exist for VHDL. However, I'm almost sure there is no open HDL simulator that supports mixed language VHDL/Verilog simulations. Maybe this is a good place to list available open HDL tools. I'm also not sure if there exist any open HVL (HW Verification Language) tool that supports decent verification language (E, Specman, Systemverilog,...). Does anyone has experience with open-HW verification? I think that we are also limited by the open-source eda tools that exist. I know there is open Verilog simulator (Icarus). I don't know which open tools exist for VHDL. However, I'm almost sure there is no open HDL simulator that supports mixed language VHDL/Verilog simulations. Maybe this is a good place to list available open HDL tools. I'm also not sure if there exist any open HVL (HW Verification Language) tool that supports decent verification language (E, Specman, Systemverilog,...). Does anyone has experience with open-HW verification?

RE: Verilog/VHDL by rfajardo on Aug 27, 2009			rfajardo Posts: 306 Joined: Jun 12, 2008 Last seen: Jan 6, 2020
Hi, Icarus Verilog support little of System Verilog. If you use verilator you can apply SystemC to verify your design. Which also enables you to use the libraries below for verification and the own SystemC Verification Library (SCV). http://www.trusster.com/ have two libraries for hardware verification, both for C++ and System Verilog. For VHDL you can use both ghdl and freehdl. I hope that gives some hint on what is available. Raul Hi, Icarus Verilog support little of System Verilog. If you use verilator you can apply SystemC to verify your design. Which also enables you to use the libraries below for verification and the own SystemC Verification Library (SCV). http://www.trusster.com/ have two libraries for hardware verification, both for C++ and System Verilog. For VHDL you can use both ghdl and freehdl. I hope that gives some hint on what is available. Raul

RE: Verilog/VHDL by arrival on Feb 1, 2010			arrival Posts: 2 Joined: Oct 14, 2008 Last seen: Jan 31, 2020
Hello, i would also like to help with RTL development, but currently my experience is vhdl only what about hdl to verilog translation tools? would that be an option? [q]Hi, Icarus Verilog support little of System Verilog. If you use verilator you can apply SystemC to verify your design. Which also enables you to use the libraries below for verification and the own SystemC Verification Library (SCV). http://www.trusster.com/ have two libraries for hardware verification, both for C++ and System Verilog. For VHDL you can use both ghdl and freehdl. I hope that gives some hint on what is available. Raul[/q] Hello, i would also like to help with RTL development, but currently my experience is vhdl only what about hdl to verilog translation tools? would that be an option? Hi, Icarus Verilog support little of System Verilog. If you use verilator you can apply SystemC to verify your design. Which also enables you to use the libraries below for verification and the own SystemC Verification Library (SCV). http://www.trusster.com/ have two libraries for hardware verification, both for C++ and System Verilog. For VHDL you can use both ghdl and freehdl. I hope that gives some hint on what is available. Raul

RE: Verilog/VHDL by tlinden on Apr 13, 2010			tlinden Posts: 1 Joined: Jun 13, 2008 Last seen: Jan 24, 2021
Altera provides a free version of ModelSim which will simulate VHDL. I believe that Xilinx does the same. However, it is a windows only tool. Altera provides a free version of ModelSim which will simulate VHDL. I believe that Xilinx does the same. However, it is a windows only tool.

RE: Verilog/VHDL by a_fezo on Apr 26, 2010			a_fezo Posts: 2 Joined: Apr 13, 2010 Last seen: May 6, 2014
[q]Hello, I am interested in joining the development and I have developed a high-performance programmable and configurable motion estimation engine mapped to an FPGA which runs under x.264. Now my work is in VHDL but I see that you have selected Verilog. Why do you want to restrict yourself to a single language?. Successful open-source projects such as the Leon3 SPARC processor include components in Verilog/VHDL and FPGA synthesis and P&R tools will compile both of them with no problems. I think to open the language to both VHDL/Verilog will be a good idea for a complex project such as this one. Regards Jose [/q] Hello, I am interested in joining the development and I have developed a high-performance programmable and configurable motion estimation engine mapped to an FPGA which runs under x.264. Now my work is in VHDL but I see that you have selected Verilog. Why do you want to restrict yourself to a single language?. Successful open-source projects such as the Leon3 SPARC processor include components in Verilog/VHDL and FPGA synthesis and P&R tools will compile both of them with no problems. I think to open the language to both VHDL/Verilog will be a good idea for a complex project such as this one. Regards Jose

RE: Verilog/VHDL by arrival on Apr 27, 2010			arrival Posts: 2 Joined: Oct 14, 2008 Last seen: Jan 31, 2020
I agree! [q][q]Hello, I am interested in joining the development and I have developed a high-performance programmable and configurable motion estimation engine mapped to an FPGA which runs under x.264. Now my work is in VHDL but I see that you have selected Verilog. Why do you want to restrict yourself to a single language?. Successful open-source projects such as the Leon3 SPARC processor include components in Verilog/VHDL and FPGA synthesis and P&R tools will compile both of them with no problems. I think to open the language to both VHDL/Verilog will be a good idea for a complex project such as this one. Regards Jose [/q] [/q] I agree! Hello, I am interested in joining the development and I have developed a high-performance programmable and configurable motion estimation engine mapped to an FPGA which runs under x.264. Now my work is in VHDL but I see that you have selected Verilog. Why do you want to restrict yourself to a single language?. Successful open-source projects such as the Leon3 SPARC processor include components in Verilog/VHDL and FPGA synthesis and P&R tools will compile both of them with no problems. I think to open the language to both VHDL/Verilog will be a good idea for a complex project such as this one. Regards Jose

RE: Verilog/VHDL by jt_eaton on Apr 27, 2010			jt_eaton Posts: 142 Joined: Aug 18, 2008 Last seen: Sep 29, 2018
[q][q]Hello, I am interested in joining the development and I have developed a high-performance programmable and configurable motion estimation engine mapped to an FPGA which runs under x.264. Now my work is in VHDL but I see that you have selected Verilog. Why do you want to restrict yourself to a single language?. Successful open-source projects such as the Leon3 SPARC processor include components in Verilog/VHDL and FPGA synthesis and P&R tools will compile both of them with no problems. I think to open the language to both VHDL/Verilog will be a good idea for a complex project such as this one. Regards Jose [/q] [/q] ------------------------------- The main problem is simulation. While it is common for real eda tools ($$$$) to support both that ability is rare among the freely available open sourced simulators. I do everything in verilog simply because icarus is a great tool but only supports verilog. You could release components as both verilog and vhdl but unless you have access to LEC ( logic equivalence checking) then ensuring that they are identical is hard. John Eaton Hello, I am interested in joining the development and I have developed a high-performance programmable and configurable motion estimation engine mapped to an FPGA which runs under x.264. Now my work is in VHDL but I see that you have selected Verilog. Why do you want to restrict yourself to a single language?. Successful open-source projects such as the Leon3 SPARC processor include components in Verilog/VHDL and FPGA synthesis and P&R tools will compile both of them with no problems. I think to open the language to both VHDL/Verilog will be a good idea for a complex project such as this one. Regards Jose ------------------------------- The main problem is simulation. While it is common for real eda tools ($$$$) to support both that ability is rare among the freely available open sourced simulators. I do everything in verilog simply because icarus is a great tool but only supports verilog. You could release components as both verilog and vhdl but unless you have access to LEC ( logic equivalence checking) then ensuring that they are identical is hard. John Eaton

RE: Verilog/VHDL by jimmy777 on Aug 10, 2010			jimmy777 Posts: 1 Joined: Jul 30, 2010 Last seen: Aug 18, 2010
hello everyone can anybody tell me where i can found the cordic alog code in vhdl for finding sine, sq root , log..etc plz do reply to this post asap i have to complete my project friends bye hello everyone can anybody tell me where i can found the cordic alog code in vhdl for finding sine, sq root , log..etc plz do reply to this post asap i have to complete my project friends bye

RE: Verilog/VHDL by ashwinbalani on Aug 10, 2010			ashwinbalani Posts: 6 Joined: Jun 30, 2010 Last seen: Oct 20, 2018
[q] Hello Jimmy, Please contact me on ashwinbalani@gmail.com to get the code for Cordic Processor in both the modes. [/q] Hello Jimmy, Please contact me on ashwinbalani@gmail.com to get the code for Cordic Processor in both the modes.

RE: Verilog/VHDL by kaushik_mallibhat on Mar 2, 2011			kaushik_mallibhat Posts: 5 Joined: Feb 11, 2011 Last seen: Aug 10, 2011
hello sir/madam can some body help me by sending verilog code to do motion estimation hello sir/madam can some body help me by sending verilog code to do motion estimation

RE: Verilog/VHDL by jamesedgar on Mar 6, 2011			jamesedgar Posts: 9 Joined: Sep 14, 2004 Last seen: Jun 26, 2020
Kaushik -- See: http://opencores.org/project,macroblock_motion_detection for verilog code to do motion estimation. There is a smaller project that uses a log search for the best match for a macroblock in a group of 9 macroblocks, and a more complicated project that uses the first project as a base and is timed to repeatedly do the same search on an entire video frame. James Kaushik -- See: http://opencores.org/project,macroblock_motion_detection for verilog code to do motion estimation. There is a smaller project that uses a log search for the best match for a macroblock in a group of 9 macroblocks, and a more complicated project that uses the first project as a base and is timed to repeatedly do the same search on an entire video frame. James

RE: Verilog/VHDL by gkamal on Mar 16, 2011			gkamal Posts: 3 Joined: Mar 14, 2011 Last seen: Apr 14, 2011
hi i am the beginner .... i have much interest in vlsi but i am lacking in basics... how can i learn concepts regarding this.. please help in improving my skills please suggest me.... hi i am the beginner .... i have much interest in vlsi but i am lacking in basics... how can i learn concepts regarding this.. please help in improving my skills please suggest me....

RE: Verilog/VHDL by kaushik_mallibhat on Mar 16, 2011			kaushik_mallibhat Posts: 5 Joined: Feb 11, 2011 Last seen: Aug 10, 2011
thank you jamesedgar. but i am using ARPS algorithm... hw can i modify this program? can u pls suggest me... thank you thank you jamesedgar. but i am using ARPS algorithm... hw can i modify this program? can u pls suggest me... thank you

RE: Verilog/VHDL by kaushik_mallibhat on Mar 16, 2011			kaushik_mallibhat Posts: 5 Joined: Feb 11, 2011 Last seen: Aug 10, 2011
gkamal I appreciate your interest. but VLSI is very vast. first be clear in which direction u r travelling to. gkamal I appreciate your interest. but VLSI is very vast. first be clear in which direction u r travelling to.

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